Suppression of Ambipolar Current and Analysis of RF Performance in Double Gate Tunneling Field Effect Transistors for Low-Power Applications

The present research letter is dedicated to a detailed analysis of a double-gate tunnel field-effect transistor (DG-TFET). The DG-TFET provides improved on-current (ION) than a conventional TFET via bandto-band (B2B) tunneling. However, DG-TFET is disadvantageous for low-power applications because of increased off-current (IOFF) due to the large ambipolar current (Iamb). In this research work, a Si/GaAs/ GaAs heterostructure DG-TFET is considered as research base for investigation of device performance. The electrical parameters of the DG-TFET device have been improved in comparison to the homostructure. The transfer (I-V) characteristics, capacitance voltage (C-V) characteristic of homo structure Si/ Si/Si and hetero structure Si/GaAs/GaAs, DG-TFET both structures is analysed comparatively. The C-V characteristics of DG-TFET have obtained using operating frequency of 1 MHz. The ambipolar current Iamb is suppressed by 5 × 108 order of magnitude in proposed Si/GaAs/GaAs hetero DG-TFET as compared to Si/Si/Si homo DG-TFET up to the applied drain voltage very low equal to VDS = 0.5 V without affecting onstate performance. The simulation result shows a very good ION/IOFF ratio (10 13) and low subthreshold slope, SS (~36.52 mV/dec). The various electrical characteristics of homo and hetero DGTFET such as on-current (ION), off current (IOFF), time delay (ιd), transconductance (gm) , and power delay product (PDP) have been improve in Si/GaAs/GaAs heterostructure DG-TFET and compared with Si/Si/ Si homo DG-TFET. The advantageous results obtained for the proposed design show its usability in the field of digital and analog applications.


Introduction
Progress in the development of low power electronics (LPEs) is reviewed by most suitable candidate named, tunneling field effect transistor popularly named Tunnel FET [1,2]. TFETs devices have emerged as a promising candidate for future low energy electronic circuit and system design. This but due their comparatively lower on-current (I ON ) must be improved to be compatible with future of VLSI circuit applications.
The Tunnel FET works by using modulated electric field by gate terminal, the width of tunneling barrier, instead of the height of a barrier that carriers must surmount via thermionic emission [9][10][11][12]. In TFET current transmission functions via tunneling transport mechanism, have weak temperature dependence and potential for subthreshold swing below the kT/q thermal limit of ~60 mV/decade at room temperature [13]. TFETs devices are not plagued by the similar short channel effects as MOSFETs. Although, the drain potential can affect the tunneling barrier at very short channel lengths, a reduction in supply voltage (V DD ) enabled by the steep subthreshold swing of a TFET can likely lessen the effect. Therefore, the TFET device structure potentially allows for scaling to shorter channel lengths prolonging Moore's Law, and these properties make TFETs a candidate for ultra-low power logic applications [13][14][15].
Owing to its distinct operation mechanism, namely band-to-band (B2B) tunneling, tunnel field effect transistors (TFETs) can overcome the subthreshold slope (SS) limitations of conventional MOSFETs and have thus attracted substantial attention for their use in low power applications. However, silicon (Si) based tunnel FETs always suffers from a low on-state current (I ON ) due large band gap (EG ~1.12eV) [16][17][18][19]. Therefore various approaches have been proposed by semiconductor device players to boost the band-to-band (B2B) tunneling current, such as using lower band-gap materials at the source or fabricating TFETs with a high-κ gate dielectric, with double-gate, with a high-κ spacer, and with a thin epitaxial tunnel layer (ETL) [20,21]. Although using, a low bandgap semiconductor materials in source terminal side, the tunnel region works to increase the tunnel current (I ON ), such devices subsequently have almost negligible off-sate current I OFF (~10 -18 A/µm). The high-κ gate dielectrics and high-κ spacers are used to enhance the electrostatics behavior of TFET devices [6,[22][23][24][25][26][27][28][29][30][31].
In this work, the ambipolar current Iamb is suppressed by 5 × 10 8 order of magnitude in proposed Si/GaAs/GaAs hetero DG -TFET as compared to Si/ Si/Si homo DG-TFET up to the applied drain voltage very low equal to VDS = 0.5 V without affecting on-state performance. The simulation result shows a very good I ON / IOFF ratio (10 13 ) and low SS (~36.52 mV/dec). The various electrical characteristics of homo and hetero structured DG-TFET such as on-current (I ON ), off-current (I OFF ), time delay (ι d ), transconductance (g m ), and power delay product (PDP) have been improve for Si/GaAs/GaAs heterostructure DG-TFET and compared with Si/Si/Si homo DG-TFET.  where BTBT mainly takes place were defined. Mesh size = 5 × 10 -4 µm at interface source/channel and mesh size = 10 -3 µm far of interface. The Newton's numerical method based on iteration was chosen to obtain a better convergence (CV). Further, to plot the figures of the high-frequency performance, a small-signal AC analysis was performed at a frequency of 1 MHz. The values adjusted to have the convergence for electron effective mass (m e ) and hole effective mass (m h ) used in the simulation are summarized on Table 2.

Device Analysis Procedure (DAP) and setup
Current conduction in TFET is governed by bandto-band (B2B) tunneling between valence bands of source to conduction band of channel. This B2B tunneling is much more sensitive to material/device parameters such as energy bandgap (E G ), dielectric thickness (t ox ), gate-dielectric materials (κ), effective mass of charge carriers (m*) of tunnel devices, followed by Eq.1 . The position of the valence and conduction bands of the intrinsic part changes with the applied gate voltage. A conduction path by The channel material with intrinsic carrier concentration n i = 1 × 10 15 cm -3 , channel thickness t Si = 10 nm and channel length as in present research work. Figure 1b having same device dimension and is structurally same as silicon TFET except GaAs is used on drain side and channel side. All the remaining device parameters and dimensions of hetero gate (hetro DG) TFET and homo gate (homo DG) TFET are listed in the Table 1. The channel (L ch ) is 50 nm, source (L s ) and drain lengths (L d ) are 100 nm. The gate oxide material thickness (t ox ) is 2 nm and the silicon film thickness (t Si ) is 10 nm. The doping levels for source, channel, and drain regions are 1 × 10 20 , 1 × 10 15 , and 5 × 10 18 cm -3 , respectively. The gate contact work function was set to be 5.   tunnel band-to-band (B2B) tunneling mechanism is then opened. The electrons can thus pass from the valance band (VB) of the p region to the conduction band (CB) of the intrinsic region and a tunnel current circulates in the device (the transistor is then in the on-state). The on-current ION of a DG-TFET, in the tunnel band-to-band (B2B) tunneling mechanism is proportional to the transmission probability T (E) of the electrons or holes by tunnel effect, which is written by mathematical expression 1.  bol ħ, e denotes reduced Planck's constant and electronic charge respectively. While, the symbol t ox and t si has been for physical oxide thickness, and semiconductor channel thickness respectively. The symbol ε ox and ε si denote dielectric constants for oxide and silicon respectively [7].
In this work, simulation is done using SILVACO The tunneling distance (λ) is determined by following mathematical expression (2). In Eq.1, m* is the effective mass and EG, is the band gap. The symbol λ denote, the tunneling distance between the source and the channel, ΔΦ denotes the band energy difference between the conduction band of source and valence band of the channel. The sym-  to the on-state, an increase in the electric field is observed [5]. It has been observed that the tun-nel barrier, λ decreases and there is a shift of the conduction band downwards. Thus, the gradual enhancement of the gate bias, VGS degrades the barrier width and causes an increased tunneling of carriers, indicated in Figure 4 and Figure 5. The simulation results indicate that, hetero double gate TFET, having smaller tunneling width λ. For hetero and homo structured double gate TFET, tunneling with λ, 0.05 µm and 0.056 µm is obtained during simulation respectively.

Result and Discussion
The tunneling barrier width λ has been reduced in case of heterostructure TFET due to lattice mismatch between Si and GaAs semiconductors at channel interface. This causes increment in tunneling current due induced stain in tunneling region. This results, the higher on-state current (I ON ) as shown in Figure 6. Figure 6 shows the transfer characteristic of DG -TFET shown in Figure 1. It has been observed from Figure 6 the comparision of transfer characteristics of homo and hetero structure DG -TFET.
From Figure 6 one can observed, the drain current, IDS increased rapidly with the drain voltage, ATLAS. In the simulation non-local B2B Tunneling model is considered for the band to band tunnel-ing of charge carrier between source and channel. Due to high doping of source band gap narrowing (BGN) model is also included, because effective bandgap directly influence the tunneling current. The Shockley-Read-Hall (SRH) recombination mod-el have been due to the presence of high impurity atom in the channel and Fermi Dirac statistics for calculating intrinsic carrier concentration. For more accurate current calculation Schenk's Trap assisted Tunneling (TAT), drift-diffusion current transport model, and Quantum Confinement (QC) models are also included. Figure 3 represent the flow chart for present research work. Figure 5 show the energy band diagram of DG -TFET. As shown in Figure 4 and Figure 5, when VGS = 0.0 V, the device is in off-state with large tunnel barrier width λ, and therefore the charge carrier, electrons do not have enough energy to move from the valance band of the source to the conduction band of the channel. On application of sufficiently high gate voltage (i.e. V GS = 1.5 V and V DS = 0.5 V), the width of tunneling barrier λ is reduced significantly and the device switches to on-state.

Figure 4 and
When the device switched from, the off-state  Table 3.
The transconductance g m represents amplification ability of device and it is defined as the slope of the transfer characteristic was used to evaluate the simulation performance of the device, the value of g m can be calculated by mathematical expression (3): As shown in Figure 8, the transconductance g m for both structures i. e. hetero and homo structures increase rapidly as external applied gate voltage V GS increases. The maximum g m value of the hetero DG-TFET heterostructure is 1.6 μS/μm and the maximum g m value of the homo DG-TFET homostructure is 1.4 μS/μm. The larger gm of hetero is larger than homostructure because the barrier width of tunneling junction decreases; the tunneling electrons increase (shown in energy band diagram Figure 4 and Figure 5). The transconductance VDS equal to 0.5 V the output current of hetero was higher than that the homostructure of the DG-TFET. Table 3, lists of the computed electrical parameters of the DG -TFET. As shown in Table  3, various electrical parameters such as on-state (ION), off-state (I OFF ), subthreshold slope (SS) and I ON /I OFF ratio have improved. While ambipolarity current I amb (A/µm) has been reduced by order of ~10 8 times. Figure 7 shows, the comparision of ambipolar property of homo and hetero structure DG-TFET. The result shows that, suppress the ambipolar current (I amb ) without deteriorating analog, and transient performance. From Figure 7, It has been ob-  structure, as shown, an increase in the capacitance from bottom to top at the threshold voltage, The Gate-Gate capacitance is mainly composed of two capacitances Gate-Drain (Cgd) and Gate-Source (Cgs), Gate-Source capacitance is lower because (g m ) of a device depends on the value of drain current IDS. So, the drain current is higher for Si/GaAs/ GaAs DG -TFET compared to DG-TFET Si/Si/Si, due to the increase of tunneling volume in the channel. Figure 9 shows the capacitance of different the presence of the tunnel effect, the Gate-Drain capacitance is a dominant capacitance due to the accumulation of the electrons of the Canal-Source and collected by the Drain region.
As an important indicator, the cut-off frequency  Another important performance parameter for RF analysis is transit time given by expression (6). According to this mathematical expression, time is inversely proportional to the cut-off frequency. If the cut-off frequency increases the transition time decreases. As a result, the speed of the heterojunction DG-TFET structure is better than that of homojunction DG-TFET, estimated cut-off frequency is smaller. Figure 12 shows the delay time versus gate applied gate voltage. From Figure 12, it can be observed that, the simulation results predicts increased delay time with increased operation gate voltage VGS. It is should be noted that the delay time is bias-dependent.
That is to say, the decrement rate of the gate voltage V GS with hetero gate double DG-TFET with smaller delay time than homo structure DG-TFET. The delay time of V GS = 2.0 V decreases rapidly.
It can be observed that, the simulation results predicts increased power delay product (PDP) with In Figure 10, as the gate voltage increases, the the cut-off frequency f T increases to reach its maximum, then with increasing Cgg it goes down, when the gate voltage V GS reaches 2.0 V the cut off frequency becomes constant. This is because the on-state current and gm value increase with the electronic B2B tunneling, the cut-off frequency of Hetero is much larger than that of homo, which can be explained by the smaller Cgg of hetero structure DG-TFET and the larger of the gm value. Table 4 resume values of f T for both structures. This observation is verified in Figure 11 that show gain band width versus gate voltage V GS . It has been observed that, the simulation results predicts decreased gate capacitance with decreased operating voltage V GS , as depicted in Figure 9 which gives the variation of the gate capacitance with V GS . It is should be noted that, the capacitances of TFET is bias-dependent. That is to say, the decrement rate of the gate capacitance with frequency is bias-dependent.
The gain bandwidth product (GBW) is anoth-  increased operation gate voltage V GS , as depicted in Figure 13, which gives the variation of the power delay product (PDP) with gate applied gate voltage V GS . It is should be noted that, the power delay product is bias-dependent. That is to say, the decrement rate of the gate voltage with hetero gate double gate with smaller power delay product (PDP). The delay time of V GS = 2.0 V decreases rapidly.

Conclusion
In the present work, 2-D TCAD Silvaco simulations are used to study the impact of heterojunction on the DC, analog and PDP. In the adopted double gate TFET design achieved on-state current of 5 × 10 -6 A/µm, I OFF of 1 × 10 -13 A/µm , SS of ~ 36 mV/decade, and maximum cut off frequency in the game of the RF also a very weak power delay product about of 1.1 × 10 -15 Watt. Also the value of delay time t d reach is obtained in picoseconds range (~ 600 Picoseconds). By using, heterojunction DG-TFET structure, it have observed the suppression of the ambipolar current I amb ~ 10 8 A/µm times. The advantageous results obtained for the proposed design show its usability in the field of digital and analog applications. These results are crucial for enabling a full and accurate assessment of TFETs through circuit predictions.